The Crossing of τ — From a Time Constant to a Yardstick for Chip Performance

τ Was Originally a Circuit Constant

In the engineering textbook, τ stands for the time constant of a first-order RC circuit — the time required for the system to reach 63.2 percent of its final value. Put more plainly: how long it takes a signal to travel from one place to another, or how long it takes a transistor to complete one switching action. The smaller τ is, the faster the response.

This is common knowledge in communications engineering. By using this symbol to name its new law, Huawei is performing an act of metaphorical return: pulling the standard for evaluating chips back from "how small the transistors are" to "how fast the signals are moving."

The Half of Moore's Law That Was Quietly Tucked Away

Over more than half a century, the semiconductor industry's understanding of "chip progress" has been almost entirely captured by a spatial narrative: make the transistors smaller, pack more circuits into the same area, and computational performance rises. This is the most popular reading of Moore's Law — every eighteen months, the transistor count doubles.

But there is more than just the quantity layer behind why transistors become more powerful after they are made smaller. There is also a more subtle change: circuit switching becomes faster.

Transistors are not ideal switches that complete the change the instant they are pressed. Switching from 0 to 1, or from 1 to 0, requires charging and discharging the small capacitances inside the circuit. The smaller the transistor, the fewer charges need to be moved, the smaller the capacitance, and the less time it takes to complete one switching action.

Placed within the framework of τ, this logic neatly explains the half of the truth that the process-narrative concealed during seventy years of semiconductor development: the spatial dimension of Moore's Law (doubling transistor count) is only one leg; the other is the temporal dimension (τ keeps falling). It is simply that the pace of transistor shrinking used to be fast enough for both legs to run at once, and no one felt the need to set τ apart.

The Process Node: From a Physical Quantity to a Brand Label

For τ to become the new yardstick, the old yardstick first has to be explained as no longer adequate.

In its original sense, the process node referred to the length of the gate on the transistor — the shorter the gate, the shorter the current channel, the more transistors the same die area could hold, and the lower the energy consumption. But from 1995 onward, the length of the gate and the process-node figure no longer had a one-to-one correspondence. Once 14nm FinFET became mainstream, chip iteration had almost nothing to do with making the gate shorter.

When we say 10nm is more advanced than 14nm, what we really mean is that the 10nm chip outperforms the 14nm chip on performance, power consumption, and cost. So long as a smaller number continues to track with Moore's-law-style gains, it counts as a useful reference even if it no longer corresponds to a real physical quantity. The process node thus gradually migrated from the physical length of the gate to a brand label — the "3nm" of different vendors is something entirely different at each.

Samsung's 3GAP+ SF3 achieves a transistor density of 190–195 MTr/mm²; TSMC's N3P reaches 224; Intel simply renamed a process that ought to be called 5nm, with a density of only 143, into Intel 3. The process node has already become a ruler whose tick marks are heavily worn. To make matters worse, once node sizes dropped below 7nm, the three goals of "more performance, less power, lower cost" stopped moving together — the returns of scaling went from a four-front assault to a single winning front.

The Four Folded Layers of τ

The core claim of the τ-Law: chip progress is no longer measured in space (the nanometer count of the process node) but in time (τ). The "time waste" inside a chip computing system is distributed across four different layers, each with its own corresponding τ.

Layer One: Transistor τ

How long it takes a transistor to switch from off to on, or from on to off. This τ is set by the transistor's own parasitic capacitance and resistance. In the past, scaling the process automatically lowered this τ, but from now on reducing τ by shrinking the transistor alone will become increasingly hard. Substitute paths include optimizing the channel material and improving the gate structure — most of the "half-generation upgrades" that phone companies have been doing come from pinching gains at this level.

Layer Two: Circuit τ

How long it takes a signal to travel from one logic unit to another. This depends on wire length and the resistance and capacitance of the interconnects. In a traditional planar layout, the two farthest-apart logic units may sit across several hundred micrometers of copper wire — the time the signal spends on that stretch easily exceeds the transistor's own switching time.

This is exactly where Logic Folding comes in.

Conventional 3D stacking takes already-completed chips and stacks them on top of one another, opening up limited vertical connections (tens of thousands to several hundred thousand) between the two layers. Logic Folding, by contrast, anticipates the vertical relationships between logic units when drafting the circuit diagram of a single chip, and lines up the units that need to talk frequently above and below one another. It is not a physical "stacking" but a restructuring of circuit-logic relations — it provides about fifty million vertical connections between two dies, two orders of magnitude more than 3D packaging.

Layer Three: Chip τ

How long it takes to move data between the processor and memory. The speed at which memory can be accessed lags seriously behind the speed at which the processor computes — this "memory wall" problem is the largest source of chip-scale τ. Network-on-chip (NoC), near-memory computing, unified memory architecture — these techniques essentially shorten the physical distance over which data must be moved, reducing chip-scale τ.

Layer Four: System τ

How long it takes for multiple chips to communicate with one another. In AI scenarios, training and inference are rarely handled by one chip alone, but by hundreds and thousands of chips working in concert. The efficiency of inter-chip connectivity determines the real compute ceiling of a system. The Hi-ONE optical interconnect and the Unify Bus (灵衢总线) that Huawei has shown on CloudMatrix 384 are both efforts to compress system-level τ.

Stacked up layer by layer, the conclusion is: all things can be measured in τ. From the picosecond-scale switching delay of a transistor to the microsecond-scale cross-chip communication delay of a data center — τ provides one optimization yardstick that can be used uniformly across twelve orders of magnitude. The breadth of view is entirely different from that of Moore's Law, which "only governs the doubling of transistor count."

Not a Master Key, but a Methodology

The τ-Law cannot replace an EUV lithography machine, and it cannot let you conjure 3nm transistors out of thin air. It supplies a framework for answering the question "where should effort go."

Under different scenarios, the bottleneck τ is completely different:

• Mobile chips fear most that peak performance is insufficient, or that power consumption and heat cannot be controlled. The τ that a phone needs to reduce is: under a limited power budget, how fast applications launch and how fast the system responds.
• Automotive chips face the sense-judge-act loop of autonomous driving. After the camera and LiDAR collect information, the chip must finish every step of processing within tens of milliseconds. The key τ here is the total time from sensor input to vehicle action.
• AI computing features hundreds and thousands of chips working together. No matter how strong a single chip's compute is, if inter-chip connectivity cannot keep up, overall compute is still constrained. The emphasis on τ here lies in connectivity efficiency.

The point of a framework is to provide a new coordinate once the old ruler has lost its validity. The chip industry will not return to the linear era of "shrink the process → double the performance," but the loop of "identify the τ bottleneck → optimize for it → keep improving system performance without process progress" is sustainable.

Verification in Numbers

Huawei has paired this methodology with physical evidence. The Kirin 2026 Logic Folding engineering sample hit 3.1 GHz on its main clock — about 12 percent faster than the 9030 Pro, an improvement larger than the sum of every step taken since the Kirin came back in 2023. The fifty million vertical connections between two dies mark a leap of two orders of magnitude over earlier 3D packaging.

At ISCAS 2026, He Tingbo cited an even broader number: from 2020 to 2026, Huawei has put 381 chips into mass production based on the τ-scaling approach. This is not a vision of the future — this is a factory already running.